The system described is the Complete Operating Capability (COC) for Data Processor Set AN/FYQ-11. The Data Processing System operates with the Integrated Control Subsystem, Large Panel Display Subsystem and Data Communications Subsystem (AUTODIN) to provide large scale automatic processing, display and transmission of information. On-line and off-line magnetic tape, card reader/punch, and line printer operations are provided by the system.
The Data Processing System provides for inputs through digital data links, integrated console typewriters, a control console, a card reader, and magnetic tapes. Outputs are provided through integrated console typewriters, integrated console printer, integrated console displays, large panel displays, line printer, control console typewriter, card punch, magnetic tapes, and digital data links.
The basic functions of input-output, data processing and storage are performed by the four major elements of the system:
|Table 1-1. L-3055 Data Processing Equipment|
Used as Data Processor Set AN/FYQ-11
|1||2||Data Processor Group OA-4580/FYQ-11 (Central Processor L-3055)|
|1||2||Disk Memory Group OA-4581/FYQ-11 (Disk Memory L-3455)|
|1||1||Buffer Processor Group OA-4592/FYQ-11 (Buffer Processor Console, four L-119 Modules)|
|2||4||Input Magnetic Tape OA-4590/FYQ-11 (Magnetic Tape Console L-3555)|
|1||4||Core Memory Group OA-4591/FYQ-11 (Core Memory L-3755)|
|1||2||Console, Data Processor Set Control OA-4654/FYQ-11 (Control Console L-3855)|
|0||1||Console, Control-Indicator OA-6041/FYQ-11 (Central Switching Console L-3655)|
|1||2||Card Reader/Punch L-3575|
|1||2||Line Printer L-3565|
|1||2||Auxiliary Disc Memory L-3456|
|1||2||Auxiliary Magnetic Tape L-3556|
Data furnished by Digital Data Links is available for computation, retrieval, and display under automatic control of stored programs and upon manual request. The system performs computations on the data, arranges the format, updates stored data, and presents the result to Integrated Consoles, Large Panel Displays, or Digital Data Links. Programs control the execution of the functions required for the operational tasks. A control program supervises the reception of messages which are to be decoded and processed for transmission or display.
Rapid processing and retrieval of a wide variety of information as well as the execution of specific programs requires close interaction between manpower and the system. Considerable scheduling and system control is necessary to establish priorities, eliminate unnecessary delays, and perform the processing operations on a dynamic real-time basis. Characteristics of the units, the data peripheral devices, and programming must be understood by personnel responsible for the programming and operation.
The Data Processing System communicates electronically with units of the system and peripheral equipment by means of trunklines, buffers, and interfaces, figure 1-2. The Disk Memory Trunkline provides for communications between the Central Processor and Disk Memory. The Uni-Record Trunkline provides for data transfer and control between the Central Processor and the Magnetic Tape Console. The Tape Transports, Line Printer, Card Punch, and the Card Reader are the Uni-Record devices which are addressed by appropriate input or output instructions. The I/O Interface provides for data transfer between the Buffer Processor or an Integrated Console Electronic Typewriter, and the Central Processor. The I/O Interface in the Central Processor selects the particular Buffer Processor Module or Integrated Console Typewriter, and designates the operation to be performed.
All data transfers are parity checked, with provision for programmed error recovery. Multiplexing of all major system elements permits maintenance with reduction, but not loss, of capability.
The program interrupt feature gives the necessary response to real-time data transfer demands. Data transfers, both input/output and with Disk Memory, have their completion signaled to the program by an interrupt.
The entire Data Processing System has been organized to provide ease of programming, speed of operation, reliability, and general purpose flexibility.
There are 43 basic commands, including input and output. Control characters and flags within the instruction word extend the range of program operations. Automatic index modification is provided with all commands that specify an operand or next-instruction address. Two index registers are static and 15 more are in the Core Memory. Indirect addressing and indirect instruction execution, with index modification, is provided.
The Central Processor may use the Core Memory in either of two special modes, PDPM (Push-Down, Pop-Up Memory), and MASM (Multi-Address Stacking Mode). Programmed memory comparisons may range over regions of Core Memory word by word, on a character field basis, independent of word boundaries.
The Central Processor operates at a frequency of 1.5 megacycles. Data transfers with the Core Memory are full-word parallel, while most other operations between registers (including addition) are in half-word parallel. Typical operation times including instruction and operand access are: addition (non-indexed) 10.5 microseconds; full word multiplication 25.0 microseconds; indexing, an additional 2.0 microseconds (static); 5.0 microseconds (from core).
A special twinning feature allows duplicate writing in a pair of individual (non-shared) memory modules.
Transfers to and from the Core Memory are word parallel, and are parity checked. The memory is time shared within the Central Processor by the real-time, Disc Memory, Uni-Record interfaces and the program control, permitting continued program execution while interface operations are in progress.
A special feature allows partial overlap of core memory cycles in separate modules, reducing the effective cycle time.
A Central Processor can be switched to one of two Disc Memory trunklines, and a trunkline can service up to seven central Disk Memory modules. Each module provides a Control Section and a fast buffer for transfers to and from the Central Processor. A Disk Memory module may, in turn, control up to seven Auxiliary Disc Memory modules, each of which also contains 20 million characters of storage but provide no Control Section or buffer storage. There may be a total of seven Central Modules and 49 Auxiliary Modules of disc storage with each Data Processor, permitting over 1 billion characters of file storage.
The Disc Memory Control Section has the important capability of accessing data by content, in addition to the standard fixed address read and write operations. A search may be specified on any combination of bit, character, and field positions in each block. Once started, the search operation continues without Central Processor intervention, and up to 1350 blocks can be compared per disc revolution. Also the Disk Memory can tag specified blocks as obsolete, and new data may then be loaded into the first available obsolete spaces, thereby reducing store access time. These blocks can be retrieved with a search by content, which, under program option, can also provide the fixed address locations.
The Buffer Processors execute their own internally stored programs. One, with appropriate program, is needed for incoming data, and another for outgoing data. Programs and data are stored on a 8000 revolution per minute magnetic disc.
The Display Consoles also have a sizable buffer storage area as part of the Disc Memory for outgoing data.
The Central Processor I/O Interface has a control section that executes operations in parallel with program execution. This I/O Interface scans input devices, Buffer Processors and Display Consoles, signaling the Central Processor with an interrupt when a message is available.
Data transfers are bit serial at a rate (over 700,000 bits per second) set by the communicating devices, and are character parity checked.
The Uni-Record Trunkline has the capability of off-line operations, namely, tape-to-card, card-to-tape, tape-to-line printer and card-to-line printer under manual control.
As part of the Disc Memory, I/O, and Uni-Record Interface operations, the Central Processor program receives an interrupt signal upon remote detection of parity error in data transfers either way. Under program control, an override of the automatic termination of data transfers upon error detection is provided as an aid in error corrections.
Blocks, as stored in the Disc Memory, have the character parity bits stripped from them, but longitudinal parity bits substituted, for reasons of speed and economy. Character parity is regenerated during transfer to the Central Processor.
A basic protection of stored data is provided by using the duplexed system to duplicate operations and stored data. This concept is carried to a finer level by the feature called "twinning", available both in Core Memory and Disc Memory. Information is simultaneously stored in duplicate when in twin mode. In event of failure of one read operation, the second copy is still available.
The normal result of a sensed error is a program interrupt, unless this interrupt is ignored. The interrupt program can then test for the detailed source of the error to take remedial action.
Each Display Console can be switched manually to either side of a duplex system. Similarly, Buffer Processors may be switched, and have duplicate standby equipment available.
Each Central Processor is able to test by program the state of each switch. In addition, special communication is available between Central Processors for programmed switching.
There are six classes of interrupts, each with an independent special program starting point. These classes are: Error, Disc Memory, Input, Real Time, Uni-Record, and Other Processor. Within each class are several detail interrupt sources which are program testable.
The Error class of interrupts has two divisions, Computer Error, which includes data transfer, arithmetic and program errors, and Interface Error, which includes Disc Memory, I/O Interface, and Uni-Record Interface errors.
The other classes of interrupts contain signals generated when specific action is to be taken, for instance, when an interface finishes a data transfer operation.
All detail interrupt requests are stored in toggles which are reset by program individually or by class, and which can also be set by program.
Other toggles, under program control, permit ignoring interrupt requests by class, subclass, or totally, but without losing interrupt requests which remain program testable.